This invention relates to programmable logic integrated circuit devices, and more particularly to programmable logic integrated circuit devices with integrated digital signal processing circuitry.
Programmable logic devices (xe2x80x9cPLDsxe2x80x9d) are well known as is shown, for example, by Jefferson et al. U.S. Pat. No. 6,215,326 and Ngai et al. U.S. Pat. No. 6,407,576. PLDs typically include many regions of programmable logic that are interconnectable in any of many different ways by programmable interconnection resources. Each logic region is programmable to perform any of several logic functions on input signals applied to that region from the interconnection resources. As a result of the logic function(s) it performs, each logic region produces one or more output signals that are applied to the interconnection resources.
The interconnection resources typically include drivers, interconnection conductors, and programmable switches for selectively making connections between various interconnection conductors. The interconnection resources can generally be used to connect any logic region output to any logic region input; although to avoid having to devote a disproportionately large fraction of the device to interconnection resources, it is usually the case that only a subset of all possible interconnections can be made in any given programmed configuration of the PLD.
One of the complexities that is faced in providing programmable logic devices involves the logic capacity of programmable logic devices. The demand for interconnection resources typically increases exponentially with respect to linear increases in logic capacity. Accordingly, interconnection arrangements that are flexible, efficient, and have sufficient signal carrying capacity are needed for programmable logic devices without displacing excessive amounts of other resources such as logic or without occupying a disproportionately larger area in PLDs.
Although only logic regions are mentioned above, it should also be noted that many PLDs also now include regions of memory that can be used as random access memory (xe2x80x9cRAMxe2x80x9d), read-only memory (xe2x80x9cROMxe2x80x9d), content addressable memory (xe2x80x9cCAMxe2x80x9d), product term (xe2x80x9cp-termxe2x80x9d) logic, etc.
As the capacity and speed of PLDs has increased, interest in using PLDs for signal or data processing tasks (e.g., for digital signal processing tasks) that may involve relatively large amounts of parallel information and may require relatively complex manipulation, combination, and recombination of that information has increased. Large numbers of signals in parallel consume a correspondingly large amount of interconnection resources; and each time that information (or another combination or recombination that includes that information) must be routed within the device, another similar large amount of the interconnection resources is consumed. Some such PLDs may be programmable to perform signal and data processing tasks that involve relatively complex manipulation, combination, and recombination of information. However, such PLDs are often deficient in providing sufficient speed of operation, sufficient logic or interconnection resources to perform additional tasks, sufficient dedicated digital signal processing circuitry and interconnection resources (e.g., multistage digital signal processing circuitry), or in providing adequate implementation of common digital signal processing tasks without impairing the operation of a substantial portion of the PLD or occupying a substantial area in the PLD.
In accordance with the principles of the present invention, programmable logic integrated circuit devices, methods, and systems may be provided that use or include digital signal processing regions. A programmable logic device may include a plurality of programmable logic regions and one or more digital signal processing regions. The regions may be arranged in different areas in the programmable logic device.
The programmable logic device may include programmable logic super-regions that may include groups of programmable logic elements, a memory region, and a digital signal processing region (e.g., a digital signal processing block). Different resources in a programmable logic device may be arranged in blocks. Each block may have a concentration of circuitry that is arranged to provide memory, programmable logic, or digital signal processing. The programmable logic device may include circuitry such as conductors and connectors for providing interconnect resources.
When a digital signal processing region is positioned in a programmable logic super-region, the digital signal processing region may use some of the local interconnect resources of the programmable logic elements, registers, and/or memory in that programmable logic super-region. Global interconnect resources of the programmable logic super-region may be used to apply input signals to the digital signal processing region and/or to route output signals out of the digital signal processing super-region.
A programmable logic device may include a column of programmable logic regions and may include a digital signal processing region in a row in that column. If desired, a programmable logic device may include a column of programmable logic regions and may include multiple rows in the column that include digital signal processing regions (e.g., each include a digital signal processing region). If desired, a programmable logic device may include a column of programmable logic regions and may include a digital signal processing region in a cell in a row in that column. The digital signal processing region may use local and global interconnect resources of an adjacent programmable logic region in the column. Such an arrangement may be used, when the digital signal processing region is approximately the same size as a programmable logic region. In some embodiments, a digital signal processing region substantially consumes the interconnect resources of an adjacent programmable logic region when the digital signal processing region is being used.
A digital signal processing region of a programmable logic device may perform multistage digital signal processing operations. A digital signal processing region of a programmable logic device may include a plurality of digital signal processing stages that are configurable to implement commonly used digital signal processing operations (e.g., commonly used filters). Multiplier circuits may be included in the digital signal processing region. Additional stages of the digital signal processing region may include stages that complement the functionality provided by the multiplier circuits. Circuitry in the additional stages may be interconnected with the multiplier circuits to implement commonly used digital signal processing operations. Additional stages may include circuitry that provides a multiply-and-add operation, a multiply-and-accumulate operation, or a multiply-and-subtract operation when used with the multiplier circuits.
The additional stages may include a stage that receives inputs from the multiplier circuits and applies an addition, a subtraction, or an accumulation operation to the received inputs. This stage may include circuits that are arranged (e.g., arranged to be dedicated) to perform addition, subtraction, and/or accumulation operations. The inputs of this stage may be dedicated to receiving outputs from the multiplier circuits. Local interconnect resources may be provided that include circuitry that is dedicated to routing the output signals of the multiplier circuits to the next stage of the digital signal processing region. Input register circuits may be included for feeding input signals to the multiplier circuits.
A next stage of the digital signal processing region may include an adder circuit. The adder circuit may perform an addition operation. The adder circuit may receive inputs from the previous stage, which may be the stage that applies an addition, a subtraction, or an accumulation operation to the outputs of the multiplier circuit stage mentioned above. The inputs of the adder circuits may be dedicated to receiving inputs from that earlier stage. Local interconnect resources may be arranged to interconnect the adder circuit and the earlier stage. Local interconnect resources may include circuitry that is dedicated to providing the output of the earlier stage to the adder circuit. The adder circuit may be used to provide a subtraction operation.
Pipeline register circuits may be arranged in between the multiplier circuits and the following stage of the digital signal processing region to apply pipeline techniques to the operation of the digital signal processing region. If desired, additional pipeline register circuits may be included as part of the multiplier circuits (i.e., inside the multiplier circuits for use in multiplier operations) and/or as part of the subsequent stages (e.g., adder circuits) to further increase the speed of operation, but which may increase latency. In embodiments in which pipeline registers are implemented, the pipeline registers may be selectable so that a user can bypass the pipeline registers if desired. The selectable pipeline registers will allow users to select whether pipeline techniques will be applied to some or all of digital signal processing operations of the digital signal processing region.
Output register circuits may be included in the digital signal processing region that register the output of the digital signal processing region. Output feedback paths may be provided from the output register circuits to an earlier stage for performing an addition operation to produce an accumulator output.
Input register circuits, output register circuits, and pipeline register circuits may include registers and may include bypass circuitry that may be used to bypass the registers. Some embodiments of the digital signal processing region may be without input register circuits, output register circuits, and/or pipeline register circuits.
A digital signal processing region for a programmable logic region may include an output selection circuit. An output selection circuit may receive input signals from a plurality of different sources in the digital signal processing region. The output selection circuits may have a number of inputs that have different bit lengths. The output selection circuit may receive inputs from different stages in the digital signal processing region. The output selection circuit may select the output of the digital signal processing region to be from one of the inputs of the output selection circuit.
A digital signal processing region for a programmable logic region may have a plurality of modes. The different modes may be selectable to provide different digital signal processing operations. Local interconnect resources may be arranged to produce different outputs in different modes. Local interconnect resources may include circuitry that routes signals between adjacent stages and may also route signals from the outputs of each stage to the output selection circuit. The output selection circuit may select the output of the digital signal processing region based on the current mode of the digital signal processing region.
The modes may include modes in which the output of the digital signal processing region is the output of one or more multipliers (e.g., four parallel nxc3x97n multipliers), is the output of the addition of multiplier outputs (e.g., the outputs of two adder circuits that each add two multiplier outputs), is the resultant of the addition of two multiplier outputs and the resultant of the subtraction of two multiplier outputs, is the output of a multiply-and-accumulate operation, is the resultant of adding three or more multiplier outputs, etc. The digital signal processing region may include circuitry that is arranged to provide the modes. If desired, the digital signal processing region may only have a single mode or only a sub-combination of the modes illustratively described herein.
A digital signal processing region for a programmable logic region may have an nxc3x97n multiplier based organization. The digital signal processing region may be reconfigurable to have an n/2xc3x97n/2 multiplier based organization. The digital signal processing region may be reconfigurable to have a 2nxc3x972n multiplier based organization. Multiplier circuits in a digital signal processing block may be configurable to operate as a single 2nxc3x972n multiplier, as multiple nxc3x97n multipliers, or as multiple n/2xc3x97n/2 multipliers. Multiplier circuits for an nxc3x97n multiplier may be structured to have the functionality to operate as multiple smaller size multipliers. For example, multiplier circuits for an nxc3x97n multiplier may support the functionality to operate as four separate n/2xc3x97n/2 multipliers. However, in implementation, routing resources for supporting all four of the n/2xc3x97n/2 multipliers may not be available. The routing resources or local interconnect resources may only support two of the four n/2xc3x97n/2 multiplier circuits. For example, in a situation where a single nxc3x97n multiplier circuit is supported with 4n bit routing resources (i.e., one n bit input for each of the multiplier inputs and a 2n bit output for the multiplier), functionality of that nxc3x97n multiplier circuit that may be available to operate as more than two n/2xc3x97n/2 multiplier circuits may not be supported because routing resources that will be needed to support more than two n/2xc3x97n/2 multiplier circuits will not available once two n/2xc3x97n/2 multiplier circuits consume the available 4n bit routing resources of the nxc3x97n multiplier circuit (i.e., four n/2 bit inputs and two n bit outputs). This example is given for a single multiplier, however, the principle is applicable in a greater scale and/or is applicable to other digital signal processing circuitry. For clarity and brevity, the multiplier circuits are primarily discussed in the context of the number of multipliers (e.g., the number of nxc3x97n multipliers, the number of n/2xc3x97n/2 multipliers, etc.) that the routing of a digital signal processing block is configured to support. The architecture of the multiplier circuits may support the functionality of additional multipliers that are not being used due to routing limitations.
Multiplier circuits in a digital signal processing block may be configured to operate as one or more pxc3x97p multipliers (p is the number of bits of each multiplier input or the precision of the input of the multiplier) and each pxc3x97p multiplier of the digital signal processing block may be configured to operate as m multipliers that each operate as a p/mxc3x97p/m multiplier where p/m equals an integer (e.g., an 18xc3x9718 multiplier may operate as two 9xc3x979 multipliers). This formula is based on the number of multipliers that are to be supported by the routing resources and does not reflect that the multiplier circuits may actually support the operation of a larger number of multipliers. Multiplier circuits that are mentioned herein may be configured to have the functionality of a particular number of multipliers wherein some or all of that particular number of multipliers are being specifically identified herein for use in digital signal processing blocks.
In some applications, decoding smaller multiplication results (e.g., n/2xc3x97n/2 multiplication results) from larger multipliers (e.g., nxc3x97n multipliers) may be inconvenient or inefficient. In those applications, dedicated multipliers (e.g., dedicated n/2xc3x97n/2 multipliers) for obtaining the results of smaller multiplication may be implemented for such use.
Each multiplier based organization of a digital signal processing region may be associated with different modes. If desired, the digital signal processing region may only have either an nxc3x97n multiplier based organization or an n/2xc3x97n/2 multiplier based organization.
One of the stages of the digital signal processing region may be an add-subtract-accumulate circuit. The add-subtract-accumulate circuit may include separate add and accumulate circuits. The add circuit may also provide a subtraction feature. In some embodiments, a feedback path to the adder circuit may be included in the add-subtract-accumulate circuit for providing accumulator operation.
In some embodiments, the add-subtract-accumulate circuit may include an adder circuit that can select a feedback path from an output of the digital signal processing region as an input. In those embodiments, the add-subtract-accumulate circuit may include an adder circuit and may include subtraction-related circuitry that is used to implement a subtraction operation using the adder circuit. The add-subtract-accumulate circuit may include accumulator-related circuitry for sign-extending one of the inputs of the add-subtract-accumulate circuit and may include additional adder circuitry that implements accumulator features. If desired, a zeroing circuit may be provided for the add-subtract-accumulate circuit that sets the feedback input to zero when the accumulator resultant is to be reset.
An output selection circuit may be included in a digital signal processing to balance the speed of operation of the digital signal processing region in different modes.
The detailed description, provided below, includes additional summary statements or descriptions that repeat, restate, append, expand, or clarify this summary.